Verification of Printer Datapaths using Timed Automata

Georgeta Igna and Frits W. Vaandrager. Verification of Printer Datapaths using Timed Automata. In T. Margaria and B. Steffen, editors. Proceedings 4th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation (ISoLA 2010), 18-20 October 2010 - Amirandes, Heraclion, Crete. LNCS 6416, pp. 412-423, Springer-Verlag, 2010.


In multiprocessor systems with many data-intensive tasks, a bus may be among the most critical resources. Typically, allocation of bandwidth to one (high-priority) task may lead to a reduction of the bandwidth of other tasks, and thereby effectively slow down these tasks. WCET analysis for this type of systems is a major research challenge. In this paper, we show how the dynamic behavior of a memory bus and a USB bus in a realistic printer application can be faithfully modeled using timed automata. We analyze, using Uppaal, the worst case latency of scan jobs with uncertain arrival times in a setting where the printer is concurrently processing an infinite stream of print jobs.


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